Not applicable.
Not applicable.
The present invention relates generally to memory devices and particularly to multiport static memory devices. More particularly, the present invention relates to detecting interport faults in static memory devices.
Fast, efficient testing is an important step in manufacturing memory chips, and the price paid for recent advances in semiconductor technology has been a lengthier and more complicated testing process. A common feature of current memories is the presence of multiple xe2x80x9cports,xe2x80x9d or gateways that allow data to be read from and/or written to the memory. The ports on a multiport memory are designed to function independently, allowing the reading or writing of data in multiple locations at the same time. Prior memories, which had a single memory port, could only read or write data in one memory location at a time. Multiple ports thus increase memory throughput, or the speed at which data can be transferred to and from memory.
FIG. 1 illustrates a representative multiport memory device 150, comprising an array of memory cells 100, 101, 109, 110, 111, 119, 190, 191 and 199. As shown in FIG. 1, the cells are organized into R rows and C columns, where R and C can be any values. Cells 100 and 101 represent the first two columns of the first row, and cell 109 represents the last (or Cxe2x88x921th) column of the first row. Similarly, cells 110, 111, and 119 represent the first, second, and last columns of the second row. In the final (or Rxe2x88x921th) row, cells 190, 191, and 199 occupy the first, second, and last columns, respectively. Each memory cell is capable of storing an electric charge, and the charges can be manipulated to store and recall data through the use of special control circuitry (not shown) in the memory 150. Each memory cell can represent one of two values, depending on whether or not the cell holds a charge. The values 1 and 0 are often used to represent the charged and uncharged states, respectively, although the reverse may be true. Because the cells can hold either of two possible values, the memory device 150 is called a xe2x80x9cbinaryxe2x80x9d device, and the cell data values are known as binary digits, or xe2x80x9cbits.xe2x80x9d
To fetch and store the data values, the memory device 150 includes xe2x80x9cword linexe2x80x9d and xe2x80x9cbit linexe2x80x9d signals that couple to the cells. The word line signals connect cells in the same row and are used to activate the cells along one row at a time. The bit line signals connect cells in the same column and are used to carry data to and from the activated cells. In a multiport device, each port has its own word lines and bit lines. The memory device 150 in FIG. 1 is shown with P ports, where P can be any number but is typically less than or equal to 11 under current technology.
The first port includes a first word line W10 that connects the cells 100, 101, and 109 in the first row; a second word line W11 that connects the cells 110, 111, and 119 in the second row; and additional word lines for the other rows, including a word line WP(Rxe2x88x921) that connects the cells 190, 191, and 199 in the final row. The first port also comprises a first bit line B10 that connects the cells 100, 110, and 190 in the first column; a second bit line B11 that connects the cells 101, 111, and 191 in the second column; and additional bit lines for the remaining columns, including a bit line BP(Cxe2x88x921) that connects the cells 109, 119, and 199 in the final column. To read data from the first row of cells through the first port, for example, the word line W10 is activated. In response to activating the word line W10, cells 100 and 101 place their data values onto bit lines B10 and B11, respectively. Similarly, the other cells in the first row drive their bit lines on the first port with the stored data, including cell 109, which drives bit line B1(Cxe2x88x921) with the data value stored in cell 109.
The word lines and bit lines also can be used to store data in the cells. To write data to the cells in the second row through the first port, for example, the word line W11 is asserted to activate the cells in the second row, including cells 110, 111, and 119. At the same time, the values being stored are placed on the bit lines belonging to the first port, including bit lines B10, B11, and B1(Cxe2x88x921). In response, the cells on the second row store the data encoded by the bit lines. Cell 110 thus stores the value of bit line B10, cell 111 stores the value of bit line B11, and cell 119 stores the value of bit line B1(Cxe2x88x921).
Similarly, the remaining ports include word lines and bit lines for accessing the memory cells. Ideally, one port can access any row of cells while another port is accessing another row of cells without interference between the two ports, since the ports do not share word lines and bit lines. In reality, however, manufacturing defects can cause one port to interfere with another port, affecting the data values that are read or written through either port. Other manufacturing defects can cause individual cells to interact unreliably. Memory defects are generally classified as cell faults, addressing faults, read/write logic faults, and interport faults.
Cells faults generally include defects known as unlinked faults, coupling faults, linked faults, neighborhood pattern sensitive faults, and complex coupling faults. Unlinked faults represent faults that occur in specific cells, without regard to a particular port or to the values of nearby cells. Types of unlinked faults include stuck-at faults, in which a cell holds a particular data value permanently; transition faults, in which a cell cannot make a transition between two values; and data retention faults, in which a cell fails to retain the correct logic value after a period of time. Table I summarizes unlinked faults.
Coupling faults represent faults in which writing a value to one cell influences the data value of another cell. Coupling faults include inversion faults, in which inverting the value of a first cell inverts the value of a second cell; idempotent faults, in which inverting the value of a first cell causes a particular value (either a 1 or a 0) to be stored in a second cell; bridging faults, in which two cells are shorted together; state faults, in which a first cell is forced to a certain value if and only if a second cell holds a particular value; and disturbance faults, in which a first cell changes value in response to a read or write operation in a second cell. Bridging faults can behave as one of two types: AND-type or OR-type. In an AND-type fault, a first cell is forced to 0 if and only if a 0 is stored in second cell. In an OR-type fault, a first cell is forced to 1 if and only if a 1 is stored in a second cell. Table II summarizes coupling faults.
Other cell faults include linked faults, neighborhood pattern sensitive faults, and complex coupling faults. Linked faults comprise multiple coupling faults which occur when three or more cells interact to form faults. A first cell, for example, may affect the value of a second cell, which affects the value of a third cell. In another linked fault scenario, the first and third cells both affect the value of the second cell. The other previously discussed cell faults, by contrast, each occur between a single pair of cells. Neighborhood pattern sensitive faults typically appear as stuck-at, transition, or two-cell coupling faults, but only occur when nearby cells are in a particular state. Complex coupling are weak coupling faults that tend to occur only when multiple ports access the memory simultaneously. Table III summarizes these other cell faults.
To access memory cells, an address value corresponding to the desired cells must be provided to the control circuitry of the memory device. In response, the control circuitry activates the desired cells by asserting the word lines that correspond to the received addresses. Addressing faults occur when no cell is accessed for a given address, multiple cells are accessed simultaneously for a single address, when a cell is not accessible, or when a cell is activated for multiple addresses. Read/write faults either prevent read and/or write operations or permanently set the memory device to read or write. Addressing faults typically stem from defects in the control circuitry, while read/write faults can be caused by defects in the control circuitry or in the individual cells.
Due to manufacturing defects such as short circuits and capacitive coupling between the ports, interport faults may occur when two or more ports access memory in parallel. Interport faults may be generally classified as word line shorts at the same row, word line shorts between adjacent rows, bit line shorts at the same column, and bit line shorts between adjacent columns. Word line shorts at the same row occur when activating a word line belonging to a first port causes the word line of a second port on the same row of memory cells to activate. For example, if word line W10 (port 1, row 0) is shorted (or connected) to word line W20 (port 2, row 0), then activating word line W10 will activate word line W20 (and vice versa) if the short behaves as an OR-type short, resulting in a word line short at the same row. If the short behaves as an AND-type short, however, then word line W10 can be activated only if word line W20 is activated at the same time, and vice versa. Word line shorts between adjacent rows happen when a word line on one port affects the word line of a different port on an adjacent row. If word line W20 (port 2, row 0) is shorted to word line W11 (port 1, row 1), for example, then activating word line W11 causes word line W20 to activate if the short behaves as an OR-type short, resulting in a word line short between rows. Similarly, an AND-type short between word lines W11 and W20 will prevent either word line from being activated unless the other word line is also activated at the same time.
Bit line shorts at the same column occur when two bit lines on different ports, but in the same column, are connected. For example, a bit line short occurs if bit line B11 (port 1, column 1) connects to bit line B21 (port 2, column 1). The result of a short between bit line B11 and B21 is that when B21 is asserted, B11 is asserted (and vice versa). Bit line shorts between columns occur when the bit line of one port is shorted to the bit line of another port in an adjacent column. If asserting bit line B11 (port 1, column 1) asserts bit line B20 (port 2, column 0), then the resulting defect is known as a bit line short between columns. Table IV summarizes the basic types of interport faults.
FIG. 2A illustrates a word line fault, using cells 100 and 110 as an example, at the first row of the memory array. As in FIG. 1, port 1 comprises word line W10 driving cell 100, word line W11 driving cell 110, and bit line B10 serving as the input/output signal for cells 100 and 110. Similarly, port 2 comprises word line W20 driving cell 100, word line W21 driving cell 110, and bit line B20 serving as the input/output signal for cells 100 and 110. Further, memory cell 100 holds a logic 0 value, and memory cell 110 holds a logic 1. As shown, a short 200 exists between word lines W10 and W20. If the short behaves as an OR-type short, then word line W20 becomes activated when word line W10 is activated, and word line W10 becomes activated if word line W20 becomes activated. In the example of FIG. 2A, a memory read operation is performed on each port. Specifically, port 1 activates word line W10 to read the value of cell 100, and port 2 activates word line W21 to read the value of cell 110. Cell 100 responds to the activation of word line W10 by placing a logic 0 onto bit line B10, and cell 110 responds to the activation of word line W21 by placing a logic 1 onto bit line B20. An OR-type short between word lines W10 and W20 activates word line W20, causing cell 100 to place a logic 0 value onto bit line B20. Thus, both cells 100 and 110 drive bit line B20 with different values, resulting in a conflict on port 2. If the short 200 behaves as an AND-type short, then word line W20, which is deactivated, prevents word line W10 from activating, thus preventing the read operation of cell 100.
FIG. 2B illustrates a word line fault between the first and second rows of the memory array, thus affecting cells 100 and 110. FIG. 2B also depicts a cell 120 on the third row of the array, coupled to word line W12 (port 1) and word line W22 (port 2). Cell 120 also couples to bit lines B10 (port 1) and B20 (port 2). As shown, memory cell 100 holds a logic 0 value, cell 110 holds a logic 1 value, and cell 120 holds a logic 0 value. A short 225 exists between word lines W20 and W11. If the short 225 behaves as an OR-type short, and if either word line W20 or word line W11 is activated, then the other word line becomes activated. If the short 225 behaves as an AND-type short, however, then neither word line W20 nor W11 can activate unless the other activates. In the example of FIG. 2B, a first read operation of cell 100 is performed on port 2 by activating word line W20, and a second read operation of cell 120 is performed on port 1 by activating word line W12 concurrently. Accordingly, cell 100 outputs a logic 0 value onto bit line B20, and cell 120 drives bit line B10 with a logic 0 value. If the short 225 behaves as an OR-type short, then word line W11 is also activated, causing cell 110 to output its logic 1 value onto bit line B10. Consequently, a conflict exists on bit line B10 between the logic 1 value output by cell 110 and the logic 0 value output by cell 120. If the short 225 behaves as an AND-type short, however, then word line W11, which is not activated, holds word line W20 low, and the read operation of cell 100 fails.
FIG. 2C illustrates a bit line fault at the same column, using cells 100 and 110 in the first column of the memory array. As shown, cell 100 holds a logic 0 value, and cell 110 holds a logic 1 value. A first read operation is performed on cell 100 through port 1 by activating word line W10, and a second read operation is performed on cell 110 through port 2 by activating word line W21. Cell 100 thus drives bit line B10 with a logic 0 value, and cell 110 drives bit line B20 with a logic 1 value. A short 250 exists between bit lines B10 and B20, however, causing bit lines B10 and B20 to always hold the same value. Because bit lines B10 and B20 are shorted together but driven with different values, the value on one of the bit lines will be incorrect. Either bit line B10 will improperly carry a logic 1 value, or bit line B20 will improperly carry a logic 0 value.
FIG. 2D illustrates a bit line fault between column 1 of the memory array, which comprises cells 100 and 110, and column 2 of the array, which includes cells 101 and 111. Cells 100 and 101 reside at row 0 of the array, coupling to word line W10 (port 1) and word line W20 (port 2). Similarly, cells 110 and 111 reside at row 1 of the array, coupled to word line W11 (port 1) and word line W21 (port 2). Cells 100 and 110 form the first column of the array, coupling to bit line B10 (port 1) and bit line B20 (port 2). Similarly, cells 101 and 111 form column 2, coupling to bit lines B11 (port 1) and B21 (port 2). Cells 100 and 101 hold logic 0 values, and cells 110 and 111 hold logic 1 values. In the example, a read operation is performed on port 2 at row 0 of the array by activating word line W20, causing cells 100 and 101 to drive bit lines B20 and B21, respectively, with logic 0 values. Similarly, a read operation is performed on port 1 at row 1 of the array by activating word line W11, causing cells 110 and 111 to drive bit lines B10 and B11, respectively, with logic 1 values. A short 275 exists, however, between bit lines B20 and B11, so that any value carried on bit line B20 is transferred to bit line B11, and vice versa. As a result, bit lines B20 and B11 are driven by both logic values 0 and 1, resulting in a bit line fault.
In the examples of FIGS. 2A-D, the shorts 200, 225, 250, and 275 resulted in conflicting values on the bit lines because some cells drove shared bit lines with conflicting values. Note that if a pair of cells drives the same bit line with the same value (i.e., if two cells place a 0 value onto a bit line), then a fault may not be apparent. For example, the short 200 between word lines W10 and W20 in FIG. 2A will not affect the output values on bit lines B10 and B20 if cells 100 and 110 hold the same value (i.e., both hold a logic 0 value or both hold a logic 1). If cells which are driving the same bit line hold different values, however, then the bit line will carry either a 0 or 1 value, depending on the nature of the short. An AND-type fault occurs when a bit line is driven with a 0 value from one cell and a 1 value from another cell, and the bit line appears to carry the 0 value (as if the conflicting values were logically AND-ed). An OR-type fault occurs when a bit line is driven with a 0 value from one cell and a 1 value from another cell, and the bit line appears to carry the logic 1 value (as if the conflicting values were logically OR-ed).
Memory faults are unacceptable, so memory devices are thoroughly tested during the manufacturing process and discarded if any faults are detected. In the last few years, various techniques have been proposed for modeling and testing memory devices. Most of these techniques deal with single-port memories and do not apply to multiport memory chips. Single port memories usually are tested using a technique called the March C algorithm, for example, or a variant of March C such as the March Cxe2x88x92, March C+, Smarch, or March LR algorithm.
The March C Algorithm includes six xe2x80x9cpasses,xe2x80x9d each of which addresses each memory cell individually. During Pass 1, March C writes a test pattern into the cells. The test pattern may be any desired sequence of bits, such as a xe2x80x9ccheckerboardxe2x80x9d pattern, but often comprises all 0""s. The 0 values can be written in any order, although the cells usually are addressed consecutively from address 0 to address Nxe2x88x921 or from address Nxe2x88x921 to address 0, where N represents the number of bits in the memory. Note also that N may represent the number of memory words, if desired, and the test may operate by addressing entire words instead of individual bits. Passes 2-5 also address each cell consecutively, executing two operations in sequence at each address. Passes 2 and 3 address the memory from address 0 to address Nxe2x88x921. During the first operation at each address in Pass 2, the test reads the current address to verify the value that was written during Pass 1. If the read operation does not return value that was written during Pass 1, then a fault is detected. The fault may have occurred either during the write operation of Pass 1 or the read operation of Pass 2 (or both). Next, the test inverts (or xe2x80x9ccomplementsxe2x80x9d) the data value of the current address. Thus, if the current cell holds a 0 value, then the test writes a 1 value to the cell, and vice versa. Similarly, the first operation of Pass 3 performs a read operation to verify the value written in Pass 2, and the second operation writes the inverted value to the cell. If the read operation returns a value different that the one written in Pass 2, then a fault is detected.
Passes 4-5 address the memory from cell Nxe2x88x921 to cell 0. The first operation in Pass 4 reads the current cell to verify the value that was written during Pass 3, and the second operation inverts the value through a write operation. Similarly, each iteration of Pass 5 first reads the value of the current cell to verify the value that was written during Pass 4 and then writes a complemented value to the cell. If the wrong value is read during any iteration of Pass 4 or Pass 5, then a fault is detected. Such a fault may have occurred during the read operation itself or during the previous write operation (or both). During Pass 6, the test reads each cell to verify the value that was written during Pass 5. As in Pass 1, the cells may be addressed in any order but preferably are accessed from address 0 to address Nxe2x88x921 or from address Nxe2x88x921 to address 0. If the wrong value is detected in any cell during Pass 6, a fault is detected. Table V summarizes the operations of the March C Algorithm in which the initial test pattern is zero for each cell.
Unfortunately, the March C algorithm cannot detect interport faults which occur in multiport memories. Though alternative techniques have been developed to detect interport faults, most of these techniques fail to detect all of the possible interport faults. Other techniques require modifications to the memory device. Such modifications, however, may be prohibitively expensive to mass produce or may prove incompatible with the needs of the end user. Still other techniques require a large number of tests, and thus extensive testing time, unless detailed structural information about the memory is known. Although some techniques have been developed to effectively test interport faults, many of these tests cover only interport faults, failing to detect other types of faults. Other techniques which cover interport faults make the assumption that all ports are read/write ports, so faults that occur between read-only ports and between write-only ports are not detected.
For the foregoing reasons, an efficient and reliable technique for detecting interport memory faults would greatly improve the manufacture and testing of memories. Such a technique, if devised, should cover all possible interport faults as well as faults that occur in single port memories, without requiring excessive testing time. Further, the technique should be applicable to any type of memory design without requiring modifications to the cell architecture and should cover read-only ports, write-only ports, and read/write ports. Despite the apparent advantages that such a technique would provide, no device or method provides these features.
Accordingly, the present invention discloses a multiport testing procedure capable of detecting faults that occur between memory ports as well as traditional cell faults. The multiport test uncovers all possible faults and covers all cells in the memory, without placing architectural constraints on the memory. While executing a test sequence on one port of the memory array (called the xe2x80x9ctest portxe2x80x9d), concurrent memory accesses are performed through other ports in the memory. If a fault exists between the port under test and any other port, then the concurrent operations interfere with the values read and/or written on the port under test, and the test uncovers the fault. Thus, the interport test requires only as many memory operations as the associated single port test, thus keeping test time to a minimum.
In one embodiment, the multiport test detects faults between the test port, which is capable of both read and write operations, and any other port, including read ports and write ports. Note that the xe2x80x9cone test portxe2x80x9d may consist of two ports, such as a read-only port combined with a write-only port, to provide both read and write functionality. The test port may also consist of at least one read/write port that is used only for read operations or only for write operations during the test. Accordingly, the test port may comprise a xe2x80x9cread test portxe2x80x9d and a xe2x80x9cwrite test port.xe2x80x9d
The multiport test comprises six passes through the memory. During Pass 1, the procedure writes a test pattern to the cells. During Passes 2-5, the test addresses each memory cell consecutively over the test port, either from address 0 to address Nxe2x88x921 or from address Nxe2x88x921 to address 0. At each cell, the test executes a read operation through the test port, to verify the data that was written during the previous pass, and then executes a write operation through the test port. The write operation inverts the value of the cell. Pass 6 again reads the cells to verify the values written during Pass 5.
During the read operation on the test port, the test executes a concurrent read operation on all other ports in the memory. The concurrent read operation occurs at the cell that is two addresses behind the test read, which corresponds to the test address xe2x88x922 if the test addresses are incrementing from 0 to Nxe2x88x921, or which corresponds to the test address +2 if the test addresses are decrementing from Nxe2x88x921 to 0. If a fault exists between the test port and any other port near the cell under test, the concurrent operation will excite the fault, possibly affecting the data value that is read from the cell. Accordingly, if the read operation returns the complement of the value that is expected, then the fault is detected.
During the write operation, the test executes concurrent read operations through all other memory ports. If the test port is formed from two separate ports, i.e., a read test port and a write test port, then the concurrent operation also occurs on the test read port. If a single port is used for both read and write operations (i.e., if the test port is a single read/write port), then the concurrent read operation does not occur on the test port. The concurrent operations occur two cells ahead of the write address. Thus, if the test address is incrementing from 0 to Nxe2x88x921, the concurrent read occurs at the test address +2. If the test address is decrementing from Nxe2x88x921 to 0, however, then the concurrent read occurs at the test address xe2x88x922. If a fault exists between the test port and any other port, then the fault may cause a write error. The write error then can be detected during a subsequent read operation.
In another embodiment, a multiport test for detecting faults between write ports comprises four memory passes. Pass 1 addresses the memory cells consecutively, writing a predetermined data pattern to the cells through the test port. At each cell, the memory test follows the write operation with a read operation at the previous cell, in order to verify the data that was written during the previous iteration. Also at each cell, the memory test performs a concurrent write in parallel with the test write. The concurrent write stores the complement of the value stored by the test write operation. Further, the concurrent write occurs on a different port than the test write, so if a fault exists between the test port and the concurrent port, then either the test write or the concurrent write fails. Pass 2 comprises reading the cells to verify the integrity of the write operations during Pass 1. If an interport fault causes a write error during Pass 1, then either the read operation of Pass 1 or the read operation of Pass 2 will detect the fault, depending on the location of the fault.
Pass 3 comprises substantially the same procedure as Pass 1, except that the data write values are complemented during Pass 3. Thus, the test write operation in Pass 3 writes the complement of the data pattern written by the test write in Pass 1, and the concurrent write operation in Pass 3 writes the complement of the data pattern written by the concurrent write during Pass 1. As in Pass 1, the test write occurs through the test port, and the concurrent write occurs through a different port, at two addresses behind the test address. Following each test write operation, the test executes a read operation one cell behind the test write operation, to verify the test write operation of the previous iteration. If the read operation returns the complement of the value written by the test write, then a fault is discovered. Pass 4 comprises reading the memory cells again to verify the write values. If a fault induces a write error in the concurrent cell during Pass 3, then Pass 4 will detect the error and, thus, the fault.
An embodiment of a memory test circuit that implements the multiport memory tests includes an address register that specifies the memory locations for all test and concurrent operations, a data register that transmits and receives data during read and write operation, a comparator that verifies data values read into the data register, and a control logic that manages operation of the other components. The address register drives a test address bus, which carries the address of each test operation, and a concurrent address bus, which carries the address of each concurrent operation. Similarly, the data register drives an internal data bus that carries data during a memory test. The test circuit also includes an address multiplexer that switches between external address lines and the internal address lines used for the test. A data multiplexer is further included for switching between the internal data lines used for the test and external data lines. The control logic asserts a test enable signal to select the state of the multiplexers, thus allowing the control logic to execute read and write operations through the multiplexers via the address and data registers.
Thus, the present invention comprises a combination of features and advantages that enable it to substantially advance the art by providing a method and apparatus for testing interport faults. These and various other characteristics and advantages of the present invention will be readily apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments of the invention and by referring to the accompanying drawings.